PIC16F1825-E/ML【PDF 5/208 页】MCU PIC 14K FLASH 1K RAM 16QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3887

1页 2页 3页 4页 [5页]6页 7页 8页 9页

127

ATmega8515(L)

2512K–AVR–01/10

When configured as a Master, the SPI interface has no automatic control of the SS line.

This must be handled by user software before communication can start. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts the 8 bits into the Slave. After shifting one byte, the SPI clock generator

stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE)

in the SPCR Register is set, an interrupt is requested. The Master may continue to shift

the next byte by writing it into SPDR, or signal the end of packet by pulling high the

Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later

use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated

as long as the SS pin is driven high. In this state, software may update the contents of

the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock

pulses on the SCK pin until the SS pin is driven low. As one byte has been completely

shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,

in the SPCR Register is set, an interrupt is requested. The Slave may continue to place

new data to be sent into SPDR before reading the incoming data. The last incoming byte

will be kept in the Buffer Register for later use.

Figure 61. SPI Master-Slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receive

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the SPI Data Register before the next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To

ensure correct sampling of the clock signal, the minimum low and high periods should

be:

Low periods: Longer than 2 CPU clock cycles.

High periods: Longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is

overridden according to Table 55. For more details on automatic port overrides, refer to

“Alternate Port Functions” on page 64.

Table 55. SPI Pin Overrides

(1)

Pin

Direction, Master SPI

Direction, Slave SPI

MOSI

User Defined

Input

MSB

MASTER

LSB

8-BIT SHIFT REGISTER

MSB

SLAVE

LSB

8-BIT SHIFT REGISTER

MISO

MOSI

SPI

CLOCK GENERATOR

SCK

MISO

MOSI

SCK

VCC

SHIFT

ENABLE

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式